1. Field of the Invention
The present invention is generally related design structures, and more specifically design structures for executing instructions in a processor.
2. Description of the Related Art
Modern computer systems typically contain several integrated circuits (ICs), including a processor which may be used to process information in the computer system. The data processed by a processor may include computer instructions which are executed by the processor as well as data which is manipulated by the processor using the computer instructions. The computer instructions and data are typically stored in a main memory in the computer system. Data being accessed and/or modified by instructions executed in the processor may also be stored in data registers in the processor. In some cases, each of the data registers in a processor may be grouped together in a bank of data registers, referred to as a register file.
Processors typically process instructions by executing the instruction in a series of small steps. In some cases, to increase the number of instructions being processed by the processor (and therefore increase the speed of the processor), the processor may be pipelined. Pipelining refers to providing separate stages in a processor where each stage performs one or more of the small steps necessary to execute an instruction. In some cases, the pipeline (in addition to other circuitry) may be placed in a portion of the processor referred to as the processor core. Some processors may have multiple processor cores, and in some cases, each processor core may have multiple pipelines. Where a processor core has multiple pipelines, groups of instructions (referred to as issue groups) may be issued to the multiple pipelines in parallel and executed by each of the pipelines in parallel.
As an example of executing instructions in a pipeline, when a first instruction is received, a first pipeline stage may process a small part of the instruction. When the first pipeline stage has finished processing the small part of the instruction, a second pipeline stage may begin processing another small part of the first instruction while the first pipeline stage receives and begins processing a small part of a second instruction. Thus, the processor may process two or more instructions at the same time (in parallel).
Where multiple instructions are executing in parallel in a pipeline, a first instruction may modify register data which is utilized by a second instruction. For example, the first instruction may load data from a data cache into a target data register, thereby overwriting register data previously stored in the data register. The second instruction may subsequently read the modified data from the data register. The second instruction may then use the modified data, for example, to perform an arithmetic operation (e.g., an addition). In some cases, the second instruction may utilize data stored in multiple registers in the register file. For example, the second instruction may use data from two registers, one for each addend of an addition operation.
In some cases, where a first instruction modifies data in a target data register which is utilized by a second instruction, the data stored in the target data register may not immediately be updated with the modified data of the first instruction. Until the modified data is written to the target data register in the register file, the target data register may contain outdated data which was previously stored in the target data register.
Because the target data register may not be immediately updated with the modified data of the first instruction, the second instruction may receive outdated data from the data register (e.g., if the second instruction attempts to access the data register contents before the data register has been updated with the modified data from the first instruction). In some cases, the outdated data may remain in the data register for several clock cycles while the modified data is maintained in the pipeline, in latches, and/or in a queue. Thus, even if the first instruction and second instruction are executed several cycles apart, the second instruction may not receive the modified data if the second instruction attempts to access the data stored in the data register.
Accordingly, what is needed is an improved method and apparatus for providing updated register data in a processor.